1. Field of the Invention
The present invention relates generally to a decoder in a mobile communication system. In particular, the present invention relates to an apparatus and method for adjusting an input range of data input to a decoder for performance improvement of a soft-decision decoder.
2. Description of the Related Art
A mobile communication system wirelessly transmits/receives data. However, because data is wirelessly transmitted/received in the mobile communication system, it is difficult for a receiver to correctly receive data transmitted from a transmitter. In order to solve this problem, the transmitter encodes transmission data before transmission, and the receiver decodes the encoded data to receive the original data.
FIG. 1 is a block diagram illustrating a structure of a general transceiver in a mobile communication system. With reference to FIG. 1, a description will be made of a structure of a transceiver in a mobile communication system.
Referring to FIG. 1, in a transmitter, input bits comprising a binary signal are input to an encoder 100. The encoder 100 encodes the input bits, and outputs coded bit streams to a matcher 102. The matcher 102 performs rate matching on the serial coded bit streams taking the number of output bits transmitted over a radio frame into consideration, and delivers the rate-matched bit streams to an interleaver 104. The interleaver 104 performs interleaving on the rate-matched bit streams such that the coded bit streams should be robust against a burst error, and outputs the interleaved bit streams to a modulator 106. The modulator 106 symbol-maps the interleaved bit streams according to a symbol mapping constellation. The modulator 106 supports Quadrature Phase Shift Keying (QPSK), 8-ary Phase Shift Keying (8PSK), 16-ary Quadrature Amplitude Modulation (16QAM) and 64QAM as its modulation scheme. The number of bits constituting the symbol is defined depending on the modulation scheme. A symbol comprises 2 bits for the QPSK modulation, 3 bits for the 8PSK modulation, 4 bits for the 16QAM modulation, and 6 bits for the 64QAM modulation. The modulated symbols output from the modulator 106 are transmitted via a transmission antenna 108.
In a receiver, symbols transmitted via the transmission antenna 108 are received by a reception antenna 110. The symbols received by the reception antenna 110 are input to a demodulator 112. The demodulator 112 has the same symbol mapping constellation as that of the modulator 106, and converts the received symbols into binary bit streams according to the symbol mapping constellation. That is, the demodulation scheme is determined by the modulation scheme. The binary bit streams demodulated by the demodulator 112 are delivered to a deinterleaver 114. The deinterleaver 114 deinterleaves the demodulated binary bit streams according to the same scheme as the interleaving scheme of the interleaver 104, and outputs the deinterleaved binary bit streams to a dematcher 116. The dematcher 116 removes repeated bits when the matcher 102 performed bit repetition, and reproduces punctured bits when the matcher 102 performed puncturing, and outputs the result bit streams to a decoder 118. The decoder 118 decodes the rate-dematched binary bit streams into binary bits.
FIG. 2 is a block diagram illustrating a structure of a general receiver using a Viterbi decoder. The receiver of FIG. 2 is made by adding a range adjuster 206 to the receiver of FIG. 1. The range adjuster will be described below. Generally, one modulation symbol output from a demodulator 200 comprises 10 bits or less. Here, a decoder 208 can estimate a signal from a transmitter with less-than-10 bits. Generally, the decoder 208 can correctly estimate a signal from the transmitter with only 3 or 4-bit information. When the number of bits input to the decoder 208 (or output from the range adjuster 206) is 3, there are 8 possible expressions. When the number of bits input to the decoder 208 is 4, there are 16 possible expressions. Table 1 illustrates possible expressions for the case where the number of bits input to the decoder 208 is 3.
TABLE 1Bits input to decoderDecimal expression100−4101−3110−2111−10000001101020113
Table 2 illustrates possible expressions for the case where the number of bits input to the decoder 208 is 4.
TABLE 2Bits input to decoderDecimal expression1000−81001−71010−61011−51100−41101−31110−21111−10000000011001020011301004010150110601117
According to Table 1, the 8 possible expressions include −4 to 3, and according to Table 2, the 16 possible expressions include −8 to 7. The range adjuster 206 has a function of adjusting an expression form of one symbol delivered to the decoder 208. A description will now be made of the reason why the range adjuster 206 adjusts an expression form of one symbol.
As described above, a binary bit stream for one symbol delivered to the range adjuster 206 is generally comprises about 10 bits, and a binary bit stream for one symbol output from the range adjuster 206 is generally comprises 3 or 4 bits. Therefore, values that cannot be expressed with the 3 or 4 bits among the input bit values should be mapped to values that can be expressed with the 3 or 4 bits. Table 3 illustrates possible expressions for the case where the number of bits input to the range adjuster 206 is 6 and the number of bits output from the range adjuster 206 is 4.
TABLE 3DecimalDecimalexpression ofexpression ofInput bitsinput bitsOutput bitsoutput bits100000−321000−8  100001−311000−8  ............111000−81000−8  111001−71001−7  ............000000000000............000110601106000111701117............01111030011170111113101117
As illustrated in Table 3, the values that cannot be expressed with the output bits are mapped to the smallest value and the largest value among the values that can be expressed with the output bits. That is, according to Table 3, when the input bit value is smaller than −8, the output bit value is expressed with −8 (1000), and when the input bit value is larger than 7, the output bit value is expressed with 7 (0111).
However, a soft-decision decoder can obtain its maximum performance when as many input values as possible can be expressed. That is, the soft-decision decoder can perform more accurate decoding when all of the input bits, including −32 (100000) and 31 (011111), are input. Therefore, it is necessary to express, with the 4 output bits, even the possible maximum value that can be expressed with the 6 input bits.
In a conventional method, an adjustment constant ‘k’ of the range adjuster is set to one fixed value so that as many input values to the soft-decision decoder as possible can be expressed, or the adjustment constant ‘k’ is adjusted according to an arithmetic mean value. However, when the range adjuster uses the one fixed value, it cannot efficiently express its input values. Referring to Table 3, when values smaller than −8 and values larger than 7 among input values to the range adjuster are more frequently input to the range adjuster as compared with other values, it is necessary to express the values smaller than −8 and the values larger than 7 in detail. For example, a method capable of distinguishing −10 and −23 should be provided. However, when the adjustment constant is fixed, there is no way to distinguish −10 and −23. Therefore, when the adjustment constant has a fixed value, the range adjuster cannot flexibly operate according to the input bit values.
Also, when the range adjuster adjusts the number of bits delivered to the decoder according to an arithmetic mean value, it has the following disadvantage. The range adjuster arithmetically averages its output bit values for a predetermined time. When the arithmetic mean value is close to −8 or 7, the adjustment constant is adjusted, and even when the arithmetic mean value is close to 0, the adjustment constant is adjusted. However, the operation of arithmetically averaging the output bit values causes an increase in memory capacity, calculations and complexity. For example, when the number of output bits is 4, 9-bit memories are required in order to perform arithmetic calculation (summation) on the output bits 128 times, increasing the complexity. In addition, in order to increase the accuracy of the arithmetic mean value, it is necessary to use a value obtained by performing arithmetic averaging calculation for a long time. However, the memory capacity increases in proportion to the number of calculations on the output bits, causing an increase in circuit complexity.